The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to a method of polishing a metal layer.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. After each layer is deposited, the layer may be etched to create circuitry features. One fabrication step involves the formation of metal vias, plugs and lines to provide conductive paths between thin film circuits. Metal vias can be created by depositing a metal layer over a patterned insulative layer and then planarizing the metal layer until the insulative layer is exposed. The portions of the metal layer remaining between the raised pattern of the insulative layer form the metal vias, plugs and lines.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a "standard" pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished (lacks small-scale roughness) and flat (lacks large-scale topography). The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad. The polishing rate sets the time needed to polish a layer. Because inadequate flatness and finish can create defective substrates, the selection of a polishing pad and slurry combination is usually dictated by the required finish and flatness. Given these constraints, the polishing time needed to achieve the required finish and flatness sets the maximum throughput of the CMP apparatus.
A reoccurring problem in metal CMP is the so-called "microscratching" of the substrate surface. Specifically, some CMP processes create shallow grooves, e.g., on the order of 500 angstroms deep, in the substrate surface. These grooves render the substrate finish unsuitable for integrated circuit fabrication, lowering the process yield.
Another problem relates to slurry waste. In some metal polishing processes, two slurries, one acidic and one alkaline, are delivered to two polishing pads in the CMP apparatus. Since the two slurries have an opposite pH, the slurry drainage system must be designed so that the slurries do not mix when they are drained from the polishing pad.